## Display Device Driver Reference for OS/2

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### EGA Register Interface Restrictions

A list of areas where restrictions apply for the EGA Register Interface are shown below:

Functions not supported
Attribute Controller registers
Sequencer Memory Mode register
Input Status registers
Graphics Controller Miscellaneous register

Functions Not Supported

Multiple display pages in graphics modes are not supported. Fonts can be loaded (by using ROM BIOS INT 10h with AH = 11h) only into Character Generator Block 0.

Attribute Controller Registers

Before your application program uses the Attribute Controller registers (I/ O address 3C0h) in an extended interrupt 10h call, it must set the flip- flop that selects the address or data register so that it selects the address register (by doing an input from I/O port 3BAh or 3DAh). The flip- flop is always reset to this state upon return from the extended INT 10h call. Interrupt routines that access the attribute chip must also leave the flip-flop set to the address register upon return from the interrupt.

Note: If the application program sets the flip-flop so that it selects the Data register, and expects the flip-flop to remain in this state, the application must disable interrupts between the time it sets the flip-flop to the Data register state and the last time the flip-flop is assumed to be in this state.

Sequencer Memory Mode Register

When the Sequencer Memory Mode register (I/O address 3C5H, data register 4) is accessed, the sequencer produces a fault on the CAS lines that can cause problems with video random access memory. As a result, the application cannot use the EGA Register Interface to read from, or write to, this register. Instead, use the following procedure to safely alter this register:

1.Disable interrupts
2.Set Synchronous Reset (bit 1) in the Sequencer Reset register to 0
3.Read/modify/write the Sequencer Memory Mode register
4.Set Synchronous Reset (bit 1) in the Sequencer Reset register to 1
5.Enable interrupts

Input Status Registers

The application cannot use the EGA Register Interface to read Input Status registers 0 (I/O address 3C2h) and 1 (I/O address 3BAh or 3DAh). If the program must read these registers, it must do so directly.

Graphics Controller Miscellaneous Register

When the Graphics Controller Miscellaneous register (I/O address 3CFh, data register 6) is accessed, a glitch on the CAS lines occurs that can cause problems with video random access memory. As a result, the application should not use the EGA Register Interface to read from or write to this register.

EGA Register Interface Function F6h does not alter the state of the Graphics Controller Miscellaneous register. Instead, use the following procedure to safely alter this register:

1.Disable interrupts
2.Set Synchronous Reset (bit 1) in the Sequencer Reset register to 0
3.Read/modify/write the Graphics Controller Miscellaneous register
4.Set Synchronous Reset (bit 1) in the Sequencer Reset register to 1
5.Enable interrupts