Makefiles

The Make utility uses a description file, or makefile, to determine what to do. In its simplest form, a makefile tells the Make utility which files depend on others and which commands need to be executed if a file changes.

targets... : dependents...
   command
      :
targets... : dependents...
   command

A makefile command can be placed on the same line as the target and dependent files by using a semicolon (;) :

targets... : dependents... ; command

A long command can span several lines. Use a backslash (\) to continue the command to the next line:

command \
   continuation of command 

Any command on a separate line must be indented by one or more spaces or tabs.

A makefile is a set of description blocks. A description block indicates the relationship among various parts of the program. It contains commands to bring all components up-to-date. The makefile can contain up to 1048 description blocks.

You can specify directories for the Make utility to search for dependent files by using the following syntax:

targets : {directory1;directory2...} dependent... 

The Make utility searches the current directory first, then directory1, directory2, and so on.

Wildcard characters (* and ?) can be used in description blocks. For example, the following description block compiles all source files with the .C extension:

ASTRO.EXE : *.C
   ICC $** 

If no commands are given in a description block, the Make utility looks for an inference rule.

Makefiles can:



Inference Rules
Pseudotargets
EXTMAKE


Targets in Several Description Blocks
Supply input to the Make Utility in a Response File
Supply input to the Make Utility from the Command Line


Make Utility Command Options